IC Design

Our engineering experience spans the complete IC design process and includes the following capabilities:

SoC design and architecture development

• Design specification generation
• Implementation analysis and risk mitigation
• System / Board / ASIC feature set definitions
• High-level modeling
• HW/SW partitioning
• Partioning for efficiency, performance, or IP reuse
• System architecture analysis
• Design prototyping

RTL Design

• Verilog
• VHDL

Design Synthesis

• RTL
• C to RTL

Functional Design Verification

• Comprehensive verification plans
• Verilog and VHDL test benches
• Constrained/Randomized test methodology (System Verilog, Specman, VERA)
• Behavioral C models
• Assertions
• Formal Verification
• Code and functional coverage assessments/metrics

Physical Design and Optimization

• Custom/hand-crafted layout
• Auto place & route
• Large digital design capacity
• Challenging timing closure
• Full chip floor planning
• Power bussing and analysis
• Static timing analysis
• Physical Verification (LVS, DRC, ERC)
• Design for Manufacturing
• Chip finishing

Design for Test

• Scan insertion
• BIST, JTAG, Test vector generation
• High-speed serial link BIST

Design for Assembly

• Coordination with package/assembly engineering
• Power planning: Power planes, flip-chip

Prototyping/Debug

• FPGA emulation
• SOC design and emulation
• Interface to foundries and assembly sub-contractors
• Interface to test development sub-contractors
• Interface to qualification and rad testing facilities
• Lab support
• Design debug

Full Custom Circuit Design

• Analog and Mixed-signal design
• High-speed circuit design (gate and transistor level)
• Full custom design and simulation